Verilog(with SV)문법 – blocking과 non-blocking assignment

// One always block, four blocking assignments. Only the statement order differs.
// q1..q3 stay inside the module; only q4 leaves it.
module chain_fwd (input clk, input d, output reg q4);
    reg q1, q2, q3;
    always @(posedge clk) begin
        q1 = d;
        q2 = q1;
        q3 = q2;
        q4 = q3;
    end
endmodule

module chain_rev (input clk, input d, output reg q4);
    reg q1, q2, q3;
    always @(posedge clk) begin
        q4 = q3;
        q3 = q2;
        q2 = q1;
        q1 = d;
    end
endmodule

module chain_mix (input clk, input d, output reg q4);
    reg q1, q2, q3;
    always @(posedge clk) begin
        q2 = q1;
        q1 = d;
        q4 = q3;
        q3 = q2;
    end
endmodule

module chain_nb (input clk, input d, output reg q4);
    reg q1, q2, q3;
    always @(posedge clk) begin
        q1 <= d;
        q2 <= q1;
        q3 <= q2;
        q4 <= q3;
    end
endmodule

$ vita --top tb_chain tb_chain.v chain.v ../syn/chain_fwd.net.v ../syn/chain_rev.net.v ../syn/chain_mix.net.v
time d  fwd rev mix nb | fwd rev mix (netlist)
  10 0   0   x   x   x |  0   x   x
  20 0   0   x   x   x |  0   x   x
  30 0   0   x   0   x |  0   x   0
  40 0   0   0   0   0 |  0   0   0
  50 1   1   0   0   0 |  1   0   0
  60 0   0   0   0   0 |  0   0   0
  70 0   0   0   1   0 |  0   0   1
  80 0   0   1   0   1 |  0   1   0
  90 0   0   0   0   0 |  0   0   0
 100 0   0   0   0   0 |  0   0   0
 110 0   0   0   0   0 |  0   0   0
simulation ended (Finish) at time 110
errors=0 warnings=0 notes=0

// Two always blocks wake on the same clk edge. Both use blocking assignments.
module race_a (input clk, input rst, output reg [3:0] cnt, output reg [3:0] snap);
    always @(posedge clk)
        if (rst) cnt = 4'd0;
        else     cnt = cnt + 4'd1;

    always @(posedge clk)
        snap = cnt;
endmodule

// The same two blocks, written in the other order.
module race_b (input clk, input rst, output reg [3:0] cnt, output reg [3:0] snap);
    always @(posedge clk)
        snap = cnt;

    always @(posedge clk)
        if (rst) cnt = 4'd0;
        else     cnt = cnt + 4'd1;
endmodule

// Nonblocking assignments in both blocks.
module race_nb (input clk, input rst, output reg [3:0] cnt, output reg [3:0] snap);
    always @(posedge clk)
        if (rst) cnt <= 4'd0;
        else     cnt <= cnt + 4'd1;

    always @(posedge clk)
        snap <= cnt;
endmodule

$ vita --top tb_race tb_race.v race.v ../syn/race_a.net.v ../syn/race_b.net.v
time  cnt/snap: race_a race_b race_nb | netlist_a netlist_b
  10            0/0    0/x    0/x   |   0/x       0/x
  20            1/1    1/0    1/0   |   1/0       1/0
  30            2/2    2/1    2/1   |   2/1       2/1
  40            3/3    3/2    3/2   |   3/2       3/2
  50            4/4    4/3    4/3   |   4/3       4/3
simulation ended (Finish) at time 50
errors=0 warnings=0 notes=0

$ iverilog -g2012 -o race.vvp -s tb_race tb_race.v race.v ../syn/race_a.net.v ../syn/race_b.net.v
$ vvp -n race.vvp
VCD info: dumpfile race.vcd opened for output.
time  cnt/snap: race_a race_b race_nb | netlist_a netlist_b
  10            0/x    0/0    0/x   |   0/x       0/x
  20            1/1    1/0    1/0   |   1/0       1/0
  30            2/1    2/2    2/1   |   2/1       2/1
  40            3/3    3/2    3/2   |   3/2       3/2
  50            4/3    4/4    4/3   |   4/3       4/3
tb_race.v:30: $finish called at 50 (1ns)

// tmp is written and read inside one always block only.
module tmp_local (input clk, input [3:0] a, b, output reg [4:0] q);
    reg [4:0] tmp;
    always @(posedge clk) begin
        tmp = a + b;
        q  <= tmp;
    end
endmodule

// A second always block also reads tmp.
module tmp_shared (input clk, input [3:0] a, b, output reg [4:0] q, output reg [4:0] r);
    reg [4:0] tmp;
    always @(posedge clk) begin
        tmp = a + b;
        q  <= tmp;
    end

    always @(posedge clk)
        r <= tmp;
endmodule

// The same two blocks, written in the other order.
module tmp_shared_b (input clk, input [3:0] a, b, output reg [4:0] q, output reg [4:0] r);
    reg [4:0] tmp;
    always @(posedge clk)
        r <= tmp;

    always @(posedge clk) begin
        tmp = a + b;
        q  <= tmp;
    end
endmodule

$ vita --top tb_tmp tb_tmp.v tmp.v ../syn/tmp_local.net.v ../syn/tmp_shared.net.v
time a+b | local q | shared q r | shared_b q r | netlist local q, shared q r
  10   2  |    2    |    2  2    |     2  x     |       2,          2  x
  20   3  |    3    |    3  3    |     3  2     |       3,          3  2
  30   4  |    4    |    4  4    |     4  3     |       4,          4  3
  40   5  |    5    |    5  5    |     5  4     |       5,          5  4
  50   6  |    6    |    6  6    |     6  5     |       6,          6  5
simulation ended (Finish) at time 50
errors=0 warnings=0 notes=0

// Saturating add: s is the 5-bit sum, y clips it to 4'hf.
// (a) nonblocking, hand-written list without s
module sat_list (input [3:0] a, b, output reg [3:0] y);
    reg [4:0] s;
    always @(a or b) begin
        s <= a + b;
        y <= s[4] ? 4'hf : s[3:0];
    end
endmodule

// (b) nonblocking, @(*)
module sat_star (input [3:0] a, b, output reg [3:0] y);
    reg [4:0] s;
    always @(*) begin
        s <= a + b;
        y <= s[4] ? 4'hf : s[3:0];
    end
endmodule

// (c) blocking, @(*)
module sat_bl (input [3:0] a, b, output reg [3:0] y);
    reg [4:0] s;
    always @(*) begin
        s = a + b;
        y = s[4] ? 4'hf : s[3:0];
    end
endmodule

$ vita --top tb_sat tb_sat.v sat.v ../syn/sat_list.net.v
time  a  b  want | (a) <= list  (b) <= @(*)  (c) = @(*) | netlist (a)
  0   3  4   7  |    x        7       7     |    7
 10   9  8  15  |    7       15      15     |   15
 20   2  2   4  |   15        4       4     |    4
 30  15  1  15  |    4       15      15     |   15
 40   5  5  10  |   15       10      10     |   10
simulation ended (Finish) at time 50
errors=0 warnings=0 notes=0

// The same 4-bit register, driven four ways by the testbench.
module dff4 (input logic clk, input logic [3:0] d, output logic [3:0] q);
    always @(posedge clk)
        q <= d;
endmodule

// (1) blocking assignment right after the rising edge
initial begin
    d_bl = 0;
    for (int i = 1; i <= 4; i++) begin
        @(posedge clk);
        d_bl = i;
    end
end

// (2) nonblocking assignment right after the rising edge
initial begin
    d_nb = 0;
    for (int i = 1; i <= 4; i++) begin
        @(posedge clk);
        d_nb <= i;
    end
end

// (3) blocking assignment on the falling edge
initial begin
    d_neg = 0;
    @(posedge clk);
    for (int i = 1; i <= 4; i++) begin
        @(negedge clk);
        d_neg = i;
        @(posedge clk);
    end
end

// '=' and '<=' on the same q, in one always block.
// (1) reset with '=', load with '<='
module mix_rst (input clk, input rst_n, input d, output reg q);
    always @(posedge clk or negedge rst_n)
        if (!rst_n) q = 1'b0;
        else        q <= d;
endmodule

// (2) load with '<=', then clear with '='
module mix_clr (input clk, input clr, input d, output reg q);
    always @(posedge clk) begin
        q <= d;
        if (clr) q = 1'b0;
    end
endmodule

// (3) the same clear written with '<=' only
module nb_clr (input clk, input clr, input d, output reg q);
    always @(posedge clk) begin
        q <= d;
        if (clr) q <= 1'b0;
    end
endmodule

$ vita --top tb_mix tb_mix.v mix.v ../syn/mix_rst.net.v ../syn/mix_clr.net.v ../syn/nb_clr.net.v
time rst_n clr | mix_rst mix_clr nb_clr | netlist: mix_rst mix_clr nb_clr
  10   1    0  |    1       1       1    |          1       0       1
  20   1    0  |    1       1       1    |          1       0       1
  30   1    1  |    1       1       0    |          1       0       0
  40   1    1  |    1       1       0    |          1       0       0
  50   1    0  |    1       1       1    |          1       0       1
simulation ended (Finish) at time 50
errors=0 warnings=0 notes=0

$ grep "assign q" ../syn/mix_clr.net.v
  assign q = 1'h0;

$ yosys -p "read_verilog ../hdl/mix.v; hierarchy -top mix_clr; dump mix_clr" \
    | awk '/^  process/{on=1} on{print} /^  end$/{if(on)exit}' | grep -v attribute
  process $proc$../hdl/mix.v:11$3
    assign { } { }
    assign { } { }
    assign $0\q[0:0] $1\q[0:0]
    switch \clr
      case 1'1
        assign { } { }
        assign $1\q[0:0] 1'0
      case 
        assign $1\q[0:0] \q
    end
    sync posedge \clk
      update \q $0\q[0:0]
  end

// (4) '<=' in a clocked block and '=' in a combinational block, same q
module mix_proc (input clk, input clr, input d, output reg q);
    always @(posedge clk)
        q <= d;
    always @(*)
        if (clr) q = 1'b0;
endmodule

$ verilator --lint-only -Wall -Wno-DECLFILENAME --timing mix_proc.v 2>&1 | grep '^%'
%Warning-MULTIDRIVENPROC: mix_proc.v:5:18: Variable written to in always block also written by another always block: 'q'
%Warning-LATCH: mix_proc.v:4:5: Latch inferred for signal 'q' (not all control paths of combinational always assign a value)
%Error-BLKANDNBLK: mix_proc.v:1:60: Unsupported: Blocking and non-blocking assignments to potentially overlapping bits of same packed variable: 'q'
%Error: Exiting due to 1 error(s), 2 warning(s)

// '=' inside always_ff: legal
module ff_bl (input logic clk, input logic [3:0] a, b, output logic [4:0] q);
    always_ff @(posedge clk) begin
        logic [4:0] tmp;
        tmp = a + b;
        q  <= tmp;
    end
endmodule

// '=' inside always_ff to a module-level variable
module ff_bl_mod (input logic clk, input logic [3:0] a, b, output logic [4:0] q);
    logic [4:0] tmp;
    always_ff @(posedge clk) begin
        tmp = a + b;
        q  <= tmp;
    end
endmodule

// '<=' inside always_comb: legal
module comb_nb (input logic [3:0] a, b, output logic [4:0] y);
    always_comb
        y <= a + b;
endmodule

// (d) nonblocking inside always_comb
module sat_comb (input logic [3:0] a, b, output logic [3:0] y);
    logic [4:0] s;
    always_comb begin
        s <= a + b;
        y <= s[4] ? 4'hf : s[3:0];
    end
endmodule

// (e) blocking inside always_comb
module sat_comb_bl (input logic [3:0] a, b, output logic [3:0] y);
    logic [4:0] s;
    always_comb begin
        s = a + b;
        y = s[4] ? 4'hf : s[3:0];
    end
endmodule

$ vvp -n satc.vvp
VCD info: dumpfile satc.vcd opened for output.
time  a  b  want | (d) always_comb <=  (e) always_comb =  (b) <= @(*) | netlist (d)
  1   3  4   7  |       x             7           7     |    7
 11   9  8  15  |       7            15          15     |   15
 21   2  2   4  |      15             4           4     |    4
 31  15  1  15  |       4            15          15     |   15
 41   5  5  10  |      15            10          10     |   10
tb_satc.sv:29: $finish called at 51 (1ns)

$ vita --top tb_satc tb_satc.sv sat_sv.sv sat.v ../syn/sat_comb.net.v
time  a  b  want | (d) always_comb <=  (e) always_comb =  (b) <= @(*) | netlist (d)
  1   3  4   7  |       7             7           7     |    7
 11   9  8  15  |      15            15          15     |   15
 21   2  2   4  |       4             4           4     |    4
 31  15  1  15  |      15            15          15     |   15
 41   5  5  10  |      10            10          10     |   10
simulation ended (Finish) at time 51
errors=0 warnings=0 notes=0

`timescale 1ns/1ns
module comb_nb_runs;
    logic [3:0] a = 4'd0, s, y;
    always_comb begin
        $display("%0t run: a=%0d s=%0d", $time, a, s);
        s <= a + 4'd1;
        y <= s;
    end
    initial begin
        #1 a = 4'd5;
        #1 $display("%0t y=%0d s=%0d", $time, y, s);
        $finish;
    end
endmodule

$ vita comb_nb_runs.sv
0 run: a=0 s=x
0 run: a=0 s=1
1 run: a=5 s=1
1 run: a=5 s=6
2 y=6 s=6
simulation ended (Finish) at time 2
errors=0 warnings=0 notes=0

$ iverilog -g2012 -o comb_nb_runs.vvp comb_nb_runs.sv 2>/dev/null
$ vvp -n comb_nb_runs.vvp
0 run: a=0 s=x
1 run: a=5 s=1
2 y=1 s=6

// '<=' to an automatic variable: illegal (IEEE 1800-2017 10.4.2)
module auto_nb (input logic clk, input logic [3:0] a, output logic [3:0] q);
    always_ff @(posedge clk) begin
        automatic logic [3:0] t;
        t <= a + 4'd1;
        q <= t;
    end
endmodule

// '<=' to a variable of an automatic task: illegal (IEEE 1800-2017 10.4.2)
module auto_task (input logic clk, input logic [3:0] a, output logic [3:0] q);
    task automatic inc(input logic [3:0] x, output logic [3:0] y);
        logic [3:0] t;
        t <= x + 4'd1;
        y = t;
    endtask
    always_ff @(posedge clk) begin
        logic [3:0] v;
        inc(a, v);
        q <= v;
    end
endmodule

$ verilator --lint-only -Wall -Wno-DECLFILENAME --timing auto_nb.sv 2>&1 | grep '^%'
%Error: auto_nb.sv:4:9: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 't'
%Error: Exiting due to 1 error(s)
$ iverilog -g2012 -o /dev/null auto_task.sv
auto_task.sv:4: error: automatically allocated variables may not be assigned values using non-blocking assignments.
1 error(s) during elaboration.

clocking cb @(posedge clk);
    default input #1step output #0;
    output d_cb;
endclocking

// (4) clocking block drive
initial begin
    d_cb = 0;
    for (int i = 1; i <= 4; i++) begin
        @(cb);
        cb.d_cb <= i;
    end
end

$ verilator --binary --timing --no-stop-fail -Wno-fatal -Wno-lint -Wno-style --Mdir obj_drive --top tb_drive tb_drive.sv
$ ./obj_drive/Vtb_drive
-Info: tb_drive.sv:72: $dumpvar ignored, as Verilated without --trace
time  q:  (1) =  (2) <=  (3) negedge  (4) clocking
  10         1      0        0             0
  20         2      1        1             1
  30         3      2        2             2
  40         4      3        3             3
  50         4      4        4             4
- tb_drive.sv:80: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 51ns; walltime 0.000 s; speed 1.500 ms/s
- Verilator: cpu 0.000 s on 1 threads; allocated 2 MB

$ iverilog -g2012 -o drive.vvp -s tb_drive tb_drive.sv 2>&1 | head -2
tb_drive.sv:53: syntax error
tb_drive.sv:53: error: Invalid module item.

`timescale 1ns/1ns
module cb_default_skew;
    logic clk = 0;
    logic [3:0] d = 0;
    always #5 clk = ~clk;
    clocking cb @(posedge clk);
        output d;   // no skew: default output skew 0
    endclocking
    initial begin   // no drive to cb.d anywhere
        #1 $display("%0t d=%0d", $time, d);
        @(cb);
        $display("%0t d=%0d", $time, d);
        #1 $display("%0t d=%0d", $time, d);
        $finish;
    end
endmodule

$ vita cb_default_skew.sv
1 d=0
5 d=x
6 d=x
simulation ended (Finish) at time 6
errors=0 warnings=0 notes=0

$ verilator --binary --timing --Mdir obj_cb --top cb_default_skew cb_default_skew.sv
$ ./obj_cb/Vcb_default_skew
1 d=0
5 d=0
6 d=0